While the large-scale integrated circuit (LSI) technology seeks for higher performances, typically to accelerate the data processing speed and to increase the data processing throughput, a number of technologies including lithography have been developed to enable fabrication of finer feature size structures. In the lithography technology, for example, the use of ArF excimer laser exposure has already succeeded in commercial fabrication of 65-nm node devices, and using the immersion lithography, further miniaturization has already been scheduled. However, a possibility is pointed out that a limit will be imposed on the enhancement of performance relying solely on miniaturization, not only from the lithography technology, but also from the technical or material aspect.
Another approach for achieving higher integration density or higher processing speed is to stack LSIs vertically to increase the integration density or processing speed. This three-dimensional (3D) semiconductor integrated circuit has attracted attention as the technology capable of increasing the integration density or processing speed independent of miniaturization, and a number of research works have already been made in the art.
The methods of stacking LSIs vertically include a method of joining LSI-bearing wafers together to form a stack, a method of attaching LSI chips on a LSI-bearing wafer to form a stack, and a method of attaching LSI chips one on top of another to form a stack. In these methods, joining LSI's together is one of key technologies, and the joint is required to be defect-free and robust.
Joining of LSI's together may be either direct or indirect joining. The direct method is to join bonding surfaces directly, and known as silicon fusion bonding or ion plasma bonding. The direct joining method can generally form a joint of high strength, which does not contain any unnecessary third material in principle, and thus has the advantage of high reliability. On the other hand, the method encounters a high technical hurdle because the bonding surfaces are required to have a high flatness and a minimal surface roughness to enable bond formation.
Among the indirect methods, the mounting technique of joining chips to form a stack has been commercially utilized, though within a limited range. For example, JP-A 2007-270125 discloses an insulating sheet of thermosetting resin which is used for forming a bond layer between chips so that a plurality of chips may be stacked.
As an example of forming a joint between wafers, WO 2004059720 (JP-A 2006-522461) discloses a process including building devices on wafers, thinning the wafers, bonding the device-built-in wafers with an insulating material, and forming electrical interconnections between the stacked wafers. The insulating/bonding material used is polyimide.
With respect to the qualities required of the material used to form a bond layer in the indirect method, JP-A 2007-270125 points out the problem that if an insulating sheet having high fluidity is used as a joint between LSI chips, it evolves gas upon curing, which causes peeling. When a bonding sheet in B stage meeting certain physical properties is used, it can be heat cured without raising the peeling problem by gas evolution.
It is pointed out in JP-A 2007-270125 that a bonding material which is heat cured with concomitant gas evolution is not suitable in the bonding of semiconductor devices as described above. Nevertheless, some materials which are preferred for embedment properties and heat stability will evolve a relatively large volume of gas upon heat curing. For example, organic silicon base materials are known to be desirable insulating materials. They have the advantage that their layers do not lose a skeleton structure even when treated at high temperatures in excess of 400° C. However, if a film having a high density of silicon oxide skeleton is to be formed, a relatively large volume of gas inevitably evolves upon heat curing. Then these materials are prone to failures by peeling or unevenness when conventional joining methods are employed.
The above and other patent documents, which are incorporated herein by reference, are listed below.
Citation List
Patent Document 1: JP-A 2007-270125
Patent Document 2: WO 2004059720 (JP-A 2006-522461)
Patent Document 3: WO 2005053009
Patent Document 4: JP-A 2005-216895
Patent Document 5: JP-A 2007-324283
Patent Document 6: JP-A 2007-314778
Patent Document 7: U.S. Pat. No. 6,268,457
Patent Document 8: JP-A 2004-311532
Patent Document 9: JP-A 2004-269693
Patent Document 10: JP-A 2004-292643
Patent Document 11: JP-A 2008-19423
Patent Document 12: JP-A H09-71654